S.A. Hareland

High performance fully-depleted tri-gate CMOS transistors

B.S. Doyle, Suman Datta, M. Doczy et al. · IEEE Electron Device Letters · 2003 · 453 citations

Engineering, Electrical Engineering, Microelectronics +15

Characterization of multi-bit soft error events in advanced SRAMs

J. Maiz, S.A. Hareland, Kedong Zhang et al. · 2004 · 244 citations

Engineering, Computer Engineering, Electrical Engineering +16

Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

Barry M. Doyle, B. I. Boyanov, Suman Datta et al. · 2004 · 219 citations

Engineering, Electrical Engineering, Microelectronics +15

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation

P. Hazucha, Tanay Karnik, J. Maiz et al. · 2004 · 153 citations

Engineering, Computer Engineering, Electrical Engineering +15

Impact of CMOS process scaling and SOI on the soft error rates of logic processes

S.A. Hareland, J. Maiz, M. Alavi et al. · 2002 · 120 citations

Engineering, Computer Engineering, Electrical Engineering +17