S.A. Hareland

High performance fully-depleted tri-gate CMOS transistors

B.S. Doyle, Suman Datta, M. Doczy et al. · IEEE Electron Device Letters · 2003 · 453 citations

Electrical Engineering, Engineering, Vlsi Design +11

Characterization of multi-bit soft error events in advanced SRAMs

J. Maiz, S.A. Hareland, Kedong Zhang et al. · 2004 · 242 citations

Hardware Security, Multi-bit Error Events, Engineering +14

Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

Barry M. Doyle, B. I. Boyanov, Suman Datta et al. · 2004 · 219 citations

Device Modeling, Electrical Engineering, Physical Design (Electronics) +11

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation

P. Hazucha, Tanay Karnik, J. Maiz et al. · 2004 · 153 citations

Low-power Electronics, Electrical Engineering, Engineering +11

Impact of CMOS process scaling and SOI on the soft error rates of logic processes

S.A. Hareland, J. Maiz, M. Alavi et al. · 2002 · 119 citations

Hardware Security, Electrical Engineering, Engineering +14