M. Alavi

A 90-nm logic technology featuring strained-silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Transactions on Electron Devices · 2004 · 654 citations

Electrical Engineering, Engineering, Nanoelectronics +10

A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell

Scott E. Thompson, N. Anand, M Armstrong et al. · 2003 · 241 citations

Nm Logic Technology, Engineering, Vlsi Design +19

Impact of CMOS process scaling and SOI on the soft error rates of logic processes

S.A. Hareland, J. Maiz, M. Alavi et al. · 2002 · 119 citations

Hardware Security, Electrical Engineering, Engineering +14

A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process

M. Alavi, M. Bohr, J. Hicks et al. · 2002 · 64 citations

Cmos Logic Process, Chemical Engineering, Electrical Engineering +15

Source/drain extension scaling for 0.1 μm and below channel length MOSFETs

Scott E. Thompson, P. Packan, T. Ghani et al. · 2002 · 50 citations

Electrical Engineering, Engineering, Vlsi Design +10