Characterization of multi-bit soft error events in advanced SRAMs

Abstract

Error correction code schemes are being implemented in memories and microprocessor caches in response to SER increases which result from increasing bit counts and technology scaling. These methods can be rendered ineffective by multi-bit error events. An exhaustive characterization of multi-bit errors in 90/130 nm SRAMs is presented to support bit interleaving rules that make the impact of multi-bit errors negligible.