A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

P. Hazucha, G. Schrom, Jaehong Hahn, +8

IEEE Journal of Solid-State Circuits

Low-power ElectronicsPmos TransistorsElectrical Engineering233-Mhz 80Engineering +13

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation

P. Hazucha, Tanay Karnik, J. Maiz, +7

Low-power ElectronicsElectrical EngineeringEngineeringNuclear PhysicsVlsi Design +9

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

P. Hazucha, Tanay Karnik, S.V. Walstra, +8

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignLocal Redundancy +10

A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

G. Schrom, P. Hazucha, Jaehong Hahn, +6

2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551)

Low-power ElectronicsDecoupling RequirementsElectrical EngineeringHysteretic ControlOn-chip 1.8 +13

Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

S. Narendra, James Tschanz, J. Hofsheier, +11

Low-power ElectronicsUltra-low Voltage CircuitsElectrical EngineeringFrequency ImprovementEngineering +9

The ZS-1 central processor

James E. Smith, G. Dermer, B. D. Vanderwarn, +5

ACM SIGARCH Computer Architecture News

Astronautics Zs-1EngineeringComputer ArchitectureProcessor ArchitectureHardware Architecture +14

1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS

S. Narendra, M. Haycock, V. Govindarajulu, +13

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

EngineeringVlsi DesignNm CmosComputer ArchitectureChip Leakage +14

Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process

P. Hazucha, Tanay Karnik, S.V. Walstra, +8

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignHardware Reliability +9

A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS

Yatin Hoskote, B. Bloechel, G. Dermer, +12

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignTcp Offload AcceleratorHigh Performance Computer NetworkComputer Architecture +21

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

Sriram Vangal, Mark Anders, Nitin Borkar, +19

IEEE Journal of Solid-State Circuits

Low-power ElectronicsHardware SecurityElectrical EngineeringEngineeringVlsi Design +11