2004 · 84 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated Circuit DesignPhysical DesignProcessor Core DesignVoltage ScalingBody BiasingCmos ScalingComplementary Metal-oxide-semiconductor BiasingLow-voltage BiasingLow-voltage Cmos DesignReverse Body BiasingUltra-low-power CmosUltra-low-voltage Circuit Design
A low-voltage swapped-body biasing technique where PMOS bodies are connected to ground and NMOS bodies to Vcc is evaluated. Available measurements show more than 2.6x frequency improvement at 0.5V Vcc and the ability to reduce Vcc by 0.2V for the same frequency compared to no body bias in 180 to 90nm CMOS technologies.
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1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS
S. Narendra, M. Haycock, V. Govindarajulu et al. · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003 · 68 citations
Engineering, Computer Engineering, Electrical Engineering +16
Standby power management for a 0.18μm microprocessor
Lawrence T. Clark, Neil Deutscher, Shay Demmons et al. · 2002 · 19 citations
Engineering, Computer Engineering, Electrical Engineering +17