V. Govindarajulu

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

Tanay Karnik, Yibin Ye, James Tschanz et al. · Proceedings - ACM IEEE Design Automation Conference · 2002 · 95 citations

Engineering, Accelerated Design, Energy Efficiency +24

1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS

S. Narendra, M. Haycock, V. Govindarajulu et al. · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003 · 68 citations

Engineering, Vlsi Design, Nm Cmos +16

Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing

James Tschanz, Yibin Ye, Liqiong Wei et al. · 2003 · 44 citations

Processor Frequency, Engineering, Vlsi Design +16

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

Sriram Vangal, Mark Anders, Nitin Borkar et al. · IEEE Journal of Solid-State Circuits · 2002 · 35 citations

Low-power Electronics, Hardware Security, Electrical Engineering +13

A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes

R. Nair, Nitin Borkar, Colin Browning et al. · 2002 · 18 citations

W Cmos Lsi, Gb/s Data Router, Engineering +14