Low-voltage Biasing
Low-Voltage Biasing is a transistor biasing technique that establishes a stable operating point for bipolar junction or field-effect transistors under supply voltages typically below 1.5 volts, distinguishing itself from conventional biasing methods by prioritizing minimal power consumption and enhanced signal integrity in low-power integrated circuit designs.
143
Publications
4.7K
Citations
625
Authors
183
Institutions
Publications per year
2017–2026
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625
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183
Intel (United States)
Santa Clara, United States
6 h-index
53 publications
3.2K citations
University of Florida
Gainesville, United States
4 h-index
5 publications
215 citations

National Taiwan University
Taipei, Taiwan
4 h-index
13 publications
173 citations
University of Catania
Catania, Italy
4 h-index
8 publications
174 citations

New Mexico State University
Las Cruces, United States
4 h-index
7 publications
208 citations
IBM (United States)
Armonk, United States
4 h-index
12 publications
586 citations
IMEC
Leuven, Belgium
3 h-index
20 publications
448 citations
National Taiwan Normal University
Taipei, Taiwan
3 h-index
3 publications
40 citations
1–8 of 183
12 publications · 614 citations
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9 publications · 237 citations
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9 publications · 298 citations
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4 publications · 107 citations
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4 publications · 189 citations
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