Low-voltage Biasing

Low-Voltage Biasing is a transistor biasing technique that establishes a stable operating point for bipolar junction or field-effect transistors under supply voltages typically below 1.5 volts, distinguishing itself from conventional biasing methods by prioritizing minimal power consumption and enhanced signal integrity in low-power integrated circuit designs.

143

Publications

4.7K

Citations

625

Authors

183

Institutions

Publications per year

2017–2026

17

Authors

625

  1. JR
    J. Ramı́rez-Angulo

    New Mexico State University, United States

    4 publications · 100 citations

    4

    h-index

  2. RC
    R.G. Carvajal

    Universidad de Sevilla, Spain

    4 publications · 100 citations

    4

    h-index

  3. SB
    Shekhar Borkar

    Intel (United States), United States

    4 publications · 229 citations

    4

    h-index

  4. AT
    A. Torralba

    Universidad de Sevilla, Spain

    3 publications · 64 citations

    3

    h-index

  5. MJ
    M. Jurczak

    IMEC, Belgium

    3 publications · 77 citations

    3

    h-index

1–5 of 625

Venues

  1. IEEE Journal of Solid-State Circuits

    12 publications · 614 citations

    12

    h-index

  2. Applied Physics Letters

    9 publications · 237 citations

    9

    h-index

  3. Electronics Letters

    9 publications · 298 citations

    9

    h-index

  4. 4

    h-index

  5. IEEE Transactions on Electron Devices

    4 publications · 189 citations

    4

    h-index

1–5