An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

Sriram Vangal, Jason Howard, Greg Ruhl, +12

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsHardware Systems +14

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS

Jason Howard, Saurabh Dighe, Yatin Hoskote, +27

Hardware SecurityElectrical EngineeringManycore ProcessorEngineeringVlsi Design +13

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

Jason Howard, Saurabh Dighe, Sriram Vangal, +13

IEEE Journal of Solid-State Circuits

EngineeringVlsi Design48-Core Ia-32 ProcessorComputer ArchitectureInterconnection Network Architecture +17

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

Shailendra Jain, Surhud Khare, Satish Yada, +18

Low-power ElectronicsHardware SecurityElectrical EngineeringEngineeringVlsi Design +10

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor

Saurabh Dighe, Sriram Vangal, Paolo Aseron, +9

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignEnergy EfficiencyPower Optimization (Eda)Nm Cmos +16

A 2 Tb/s 6<formula formulatype="inline"><tex Notation="TeX">$\,\times\,$</tex> </formula>4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS

Praveen Salihundam, Shailendra Jain, Tiju Jacob, +5

IEEE Journal of Solid-State Circuits

Tb/s 6Flow ControlVlsi DesignEngineeringHigh Performance Computer Network +14

Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

S. Narendra, James Tschanz, J. Hofsheier, +11

Low-power ElectronicsUltra-low Voltage CircuitsElectrical EngineeringFrequency ImprovementEngineering +9

1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS

S. Narendra, M. Haycock, V. Govindarajulu, +13

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

EngineeringVlsi DesignNm CmosComputer ArchitectureChip Leakage +14

Selective node engineering for chip-level soft error rate improvement [in CMOS]

Tanay Karnik, Sriram Vangal, V. Veeramachaneni, +3

Hardware SecurityElectrical EngineeringPhysical Design (Electronics)EngineeringVlsi Design +11

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor

Saurabh Dighe, Paolo Aseron, Sunil Kumar, +8

Optimal Core MappingManycore ProcessorEngineeringVlsi DesignEnergy Efficiency +13