Shailendra Jain

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

Sriram Vangal, Jason Howard, Gregory Ruhl et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 2007 · 633 citations

Hardware Security, System On Chip, Electrical Engineering +14

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

Sriram Vangal, Jason Howard, Greg Ruhl et al. · IEEE Journal of Solid-State Circuits · 2008 · 625 citations

Engineering, Vlsi Design, Computer Architecture +16

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS

Jason Howard, Saurabh Dighe, Yatin Hoskote et al. · 2010 · 597 citations

Hardware Security, Electrical Engineering, Manycore Processor +15

A Novel Multilevel Inverter Based on Switched DC Sources

Krishna Kumar Gupta, Shailendra Jain · IEEE Transactions on Industrial Electronics · 2013 · 426 citations

Novel Multilevel Inverter, Electrical Engineering, Engineering +7

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

Jason Howard, Saurabh Dighe, Sriram Vangal et al. · IEEE Journal of Solid-State Circuits · 2010 · 390 citations

Engineering, Vlsi Design, 48-Core Ia-32 Processor +19