A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

TLDR

The paper introduces a 48‑core IA‑32 processor featuring a 64‑node 2D‑mesh network‑on‑chip with four DDR3 memory channels and an integrated voltage regulator controller. The study aims to present the design and performance characteristics of this 48‑core processor. Each mesh node hosts a five‑port virtual cut‑through router shared by two IA‑32 cores, enabling message‑passing communication and 384 KB on‑die shared memory, while 8 voltage and 28 frequency islands provide fine‑grained DVFS across cores and the mesh. At a nominal 1.1 V supply, the cores run at 1 GHz and the mesh at 2 GHz, with power dissipation ranging from 25 W to 125 W as voltage and performance scale; the design uses 45 nm Hi‑K CMOS and contains 1.3 billion transistors.

Abstract

This paper describes a multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 64 2D-mesh network-on-chip architecture. Located at each mesh node is a five-port virtual cut-through packet-switched router shared between two IA-32 cores. Core-to-core communication uses message passing while exploiting 384 KB of on-die shared memory. Fine grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. At the nominal 1.1 V supply, the cores operate at 1 GHz while the 2D-mesh operates at 2 GHz. As performance and voltage scales, the processor dissipates between 25 W and 125 W. The processor is implemented in 45 nm Hi-K CMOS and has 1.3 billion transistors.