The Contribution of Low-Energy Protons to the Total On-Orbit SEU Rate

Nathaniel A. Dodds, M.J. Martinez, P.E. Dodd, +31

IEEE Transactions on Nuclear Science

EngineeringNuclear PhysicsSecondary ProtonsLow-energy ProtonsRadiation Protection +16

Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology

K. Lilja, M. Bounasser, Shi-Jie Wen, +6

IEEE Transactions on Nuclear Science

Heavy-ion Single-event MeasurementsEngineeringVlsi DesignFlip-flop DesignsComputer Architecture +16

Electron-Induced Single-Event Upsets in Static Random Access Memory

M. King, Robert A. Reed, Robert A. Weller, +20

IEEE Transactions on Nuclear Science

Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology

S. Jagannathan, T. D. Loveless, B. L. Bhuva, +6

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignUpset MechanismNanoelectronics40-Nm Cmos Technology +14

Effect of Transistor Density and Charge Sharing on Single-Event Transients in 90-nm Bulk CMOS

N. M. Atkinson, Jonathan R. Ahlbin, Arthur F. Witulski, +6

IEEE Transactions on Nuclear Science

Device ModelingLow-power ElectronicsElectrical EngineeringSe Cross SectionEngineering +13

Effectiveness of SEL Hardening Strategies and the Latchup Domino Effect

Nathaniel A. Dodds, Nicholas C. Hooten, Robert A. Reed, +14

IEEE Transactions on Nuclear Science

Hardware SecurityElectrical EngineeringSel Hardening StrategiesEngineeringVlsi Design +9

Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections

N. J. Gaspard, S. Jagannathan, Z. J. Diggins, +11

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignNuclear PhysicsComputer ArchitectureIon Beam Instrumentation +15

On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

T. D. Loveless, J. S. Kauppila, S. Jagannathan, +12

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignMeasurementOn-chip MeasurementEducation +16

Impact of Supply Voltage and Frequency on the Soft Error Rate of Logic Circuits

N. N. Mahatme, N. J. Gaspard, S. Jagannathan, +6

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignComputer ArchitectureHardware SecurityCircuit System +14

Impact of technology scaling on the combinational logic soft error rate

N. N. Mahatme, N. J. Gaspard, T. Assis, +7

Hardware SecurityLogic SynthesisElectrical EngineeringEngineeringVlsi Design +13