T. D. Loveless

Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

N. N. Mahatme, S. Jagannathan, T. D. Loveless et al. · IEEE Transactions on Nuclear Science · 2011 · 146 citations

Engineering, Vlsi Design, Computer Architecture +20

Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node

T. D. Loveless, S. Jagannathan, Trey Reece et al. · IEEE Transactions on Nuclear Science · 2011 · 123 citations

Engineering, Dice Designs, Neutron Scattering +16

A Hardened-by-Design Technique for RF Digital Phase-Locked Loops

T. D. Loveless, L. W. Massengill, B. L. Bhuva et al. · IEEE Transactions on Nuclear Science · 2006 · 104 citations

Electrical Engineering, Digital Phase-locked Loops, Engineering +15

A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS

T. D. Loveless, L. W. Massengill, B. L. Bhuva et al. · IEEE Transactions on Nuclear Science · 2007 · 94 citations

Low-power Electronics, Hardware Security, Electrical Engineering +10

Modeling and Mitigating Single-Event Transients in Voltage-Controlled Oscillators

T. D. Loveless, L. W. Massengill, W.T. Holman et al. · IEEE Transactions on Nuclear Science · 2007 · 78 citations

Electrical Engineering, Pll Designs, Vlsi Design +14