S. Jagannathan

Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

N. N. Mahatme, S. Jagannathan, T. D. Loveless et al. · IEEE Transactions on Nuclear Science · 2011 · 146 citations

Engineering, Vlsi Design, Computer Architecture +20

Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node

T. D. Loveless, S. Jagannathan, Trey Reece et al. · IEEE Transactions on Nuclear Science · 2011 · 123 citations

Engineering, Dice Designs, Neutron Scattering +16

Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology

K. Lilja, M. Bounasser, Shi-Jie Wen et al. · IEEE Transactions on Nuclear Science · 2013 · 74 citations · Full text

Heavy-ion Single-event Measurements, Engineering, Vlsi Design +18

Independent Measurement of SET Pulse Widths From N-Hits and P-Hits in 65-nm CMOS

S. Jagannathan, Matthew J. Gadlage, B. L. Bhuva et al. · IEEE Transactions on Nuclear Science · 2010 · 59 citations

Set Pulse Widths, Electrical Engineering, Engineering +15

Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology

S. Jagannathan, T. D. Loveless, B. L. Bhuva et al. · IEEE Transactions on Nuclear Science · 2012 · 58 citations

Engineering, Vlsi Design, Upset Mechanism +16