Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

N. N. Mahatme, S. Jagannathan, T. D. Loveless, +4

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignComputer ArchitectureRecurrent Neural NetworkHardware Security +18

Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node

T. D. Loveless, S. Jagannathan, Trey Reece, +7

IEEE Transactions on Nuclear Science

EngineeringDice DesignsNeutron ScatteringNm Bulk TechnologiesAdvanced Packaging (Semiconductors) +14

Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology

K. Lilja, M. Bounasser, Shi-Jie Wen, +6

IEEE Transactions on Nuclear Science

Heavy-ion Single-event MeasurementsEngineeringVlsi DesignFlip-flop DesignsComputer Architecture +16

Independent Measurement of SET Pulse Widths From N-Hits and P-Hits in 65-nm CMOS

S. Jagannathan, Matthew J. Gadlage, B. L. Bhuva, +5

IEEE Transactions on Nuclear Science

Set Pulse WidthsElectrical EngineeringEngineeringPhysicsMeasurement +13

Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology

S. Jagannathan, T. D. Loveless, B. L. Bhuva, +6

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignUpset MechanismNanoelectronics40-Nm Cmos Technology +14

Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections

N. J. Gaspard, S. Jagannathan, Z. J. Diggins, +11

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignNuclear PhysicsComputer ArchitectureIon Beam Instrumentation +15

On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

T. D. Loveless, J. S. Kauppila, S. Jagannathan, +12

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignMeasurementOn-chip MeasurementEducation +16

Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology

S. Jagannathan, T. D. Loveless, B. L. Bhuva, +5

IEEE Transactions on Nuclear Science

Hardware SecurityLow-power ElectronicsElectrical EngineeringEngineeringVlsi Design +11

Impact of Supply Voltage and Frequency on the Soft Error Rate of Logic Circuits

N. N. Mahatme, N. J. Gaspard, S. Jagannathan, +6

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignComputer ArchitectureHardware SecurityCircuit System +14

Impact of technology scaling on the combinational logic soft error rate

N. N. Mahatme, N. J. Gaspard, T. Assis, +7

Hardware SecurityLogic SynthesisElectrical EngineeringEngineeringVlsi Design +13