22-nm fully-depleted tri-gate CMOS transistors

Abstract

At the 22-nm technology node, fully-depleted tri-gate transistors were introduced for the first time on a high-volume manufacturing process. Fabricated on a bulk silicon substrate, these transistors feature a third-generation high-k + metal-gate technology and a fifth generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (~70 mV/decade) and very low DIBL (~50 mV/V) values that are critical for low voltage operation. Self-aligned contacts are implemented along with the tri-gate transistors to eliminate restrictive contact-to-gate registration requirements from scaling the gate pitch. This enables an SRAM cell size of 0.092 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . High yield and reliability have been demonstrated on multiple microprocessors.