Subthreshold Cmos Design
Subthreshold CMOS Design is a circuit design methodology that belongs to the class of low-power integrated circuit techniques and is distinguished by its operation of CMOS transistors in the subthreshold region, where the gate-to-source voltage is below the threshold voltage, enabling ultralow power consumption at the expense of reduced speed and increased susceptibility to process variations.
226
Publications
13.3K
Citations
685
Authors
211
Institutions
Publications per year
2017–2026
30
Parents
226
1–5 of 226
685
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Massachusetts Institute of Technology, United States
7 publications · 2K citations
7
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7
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1–5 of 685
211

Johns Hopkins University
Baltimore, United States
11 h-index
23 publications
2.4K citations
Massachusetts Institute of Technology
Cambridge, United States
10 h-index
27 publications
4.2K citations
California Institute of Technology
Pasadena, United States
8 h-index
14 publications
824 citations
University of Michigan
Ann Arbor, United States
8 h-index
30 publications
1.7K citations
Purdue University West Lafayette
West Lafayette, United States
7 h-index
16 publications
3.5K citations

Hokkaido University
Sapporo, Japan
7 h-index
25 publications
1.8K citations

University of Calabria
Rende, Italy
7 h-index
21 publications
1.7K citations

University of Oslo
Oslo, Norway
7 h-index
16 publications
337 citations
1–8 of 211
18 publications · 3.5K citations
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13 publications · 570 citations
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11 publications · 750 citations
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12 publications · 964 citations
12
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11 publications · 351 citations
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