Subthreshold Cmos Design

Subthreshold CMOS Design is a circuit design methodology that belongs to the class of low-power integrated circuit techniques and is distinguished by its operation of CMOS transistors in the subthreshold region, where the gate-to-source voltage is below the threshold voltage, enabling ultralow power consumption at the expense of reduced speed and increased susceptibility to process variations.

226

Publications

13.3K

Citations

685

Authors

211

Institutions

Publications per year

2017–2026

30

Authors

685

  1. AG
    Andreas G. Andreou

    Johns Hopkins University, United States

    11 publications · 971 citations

    11

    h-index

  2. TH
    Tetsuya Hirose

    Kobe University, Japan

    7 publications · 827 citations

    7

    h-index

  3. TA
    Tetsuya Asai

    Hokkaido University, Japan

    7 publications · 603 citations

    7

    h-index

  4. AP
    Anantha P. Chandrakasan

    Massachusetts Institute of Technology, United States

    7 publications · 2K citations

    7

    h-index

  5. DS
    Dennis Sylvester

    University of Michigan, United States

    7 publications · 413 citations

    7

    h-index

1–5 of 685

Venues

  1. IEEE Journal of Solid-State Circuits

    18 publications · 3.5K citations

    17

    h-index

  2. 13

    h-index

  3. 12

    h-index

  4. IEEE Transactions on Electron Devices

    12 publications · 964 citations

    12

    h-index

  5. Electronics Letters

    11 publications · 351 citations

    11

    h-index

1–5