The effective drive current in CMOS inverters

Abstract

A simple but accurate expression for the effective drive current, I/sub eff/, for CMOS inverter delay is obtained. We show that the choice I/sub eff/=(I/sub H/+I/sub L/)/2, where I/sub L/=I/sub ds/(V/sub gs/=V/sub dd//2,V/sub ds/=V/sub dd/), and I/sub H/=I/sub ds/(V/sub gs/=V/sub dd/,V/sub ds/=V/sub dd//2) is defined, accurately predicts inverter delay when tested against compact models over a variety of conditions and against hardware results in 90 nm node technology. Furthermore, this definition of I/sub eff/ accurately captures the delay behavior of non-traditionally scaled devices, where mobility and V/sub T//V/sub dd/ are scaled in neither a regular nor uniform manner.