Analysis of encapsulation process in 3D stacked chips with different microbump array

Demystifying 3D ICs: The Pros and Cons of Going Vertical

W. Rhett Davis, John Wilson, Stephen Mick et al. · IEEE Design & Test of Computers · 2005 · 827 citations

Crosstalk Tolerances, Available 3D, Engineering +26

Reliability challenges in 3D IC packaging technology

K. N. Tu · Microelectronics Reliability · 2010 · 622 citations

Reliability, 3D Ic Architecture, Chip-scale Package +7

Overview and outlook of through‐silicon via (TSV) and 3D integrations

John H. Lau · Microelectronics International · 2011 · 324 citations

Engineering, Device Integration, Ic Integration Sip +17

Three-Dimensional Modeling of Mold Filling in Microelectronics Encapsulation Process

R. Y. Chang, Wenli Yang, S.-J. Hwang et al. · IEEE Transactions on Components and Packaging Technologies · 2004 · 73 citations

Engineering, Mechanical Engineering, Advanced Manufacturing +17

3D integration review

Mukta Farooq, Subramanian S. Iyer · Science China Information Sciences · 2011 · 46 citations

Geometric Modeling, 3D Ic Architecture, Engineering +9