Impact of Strained-Si PMOS Transistors on SRAM Soft Error Rates

Abstract

For advanced deep sub-micron technology nodes, the use of strained-Si is fast becoming the norm. The experimental Soft Error Rate of 40 nm technology Deep-N-well SRAMs that incorporate strained-Si PMOS transistors are compared with the SER for 90 nm, 65 nm and 45 nm Deep-N-Well bulk CMOS SRAMs fabricated without strain. Results indicate that the total SER decreases by approximately 50% with strain. Most importantly, however, the Multiple-Cell Upset Rate decreases significantly. The factors that result in improved SER for strained SRAMs are investigated.