Impact of CMOS technology scaling on the atmospheric neutron soft error rate

TLDR

The study examined how atmospheric neutron soft error rates scale with CMOS feature size, impacting circuit reliability at ground and flight altitudes. The analysis focused on bulk CMOS devices built on lightly doped p‑type wafers. Empirical modeling shows SER per bit decreases linearly with feature size, while MBGR predicts an even steeper decline, and when accounting for the growing number of bits, SER per chip does not rise faster than linearly as feature size shrinks.

Abstract

We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight altitudes. We considered CMOS circuits manufactured in a bulk process with a lightly-doped p-type wafer. One method, based on the empirical model, predicts a linear decrease of SER per bit with decreasing feature size L/sub G/. A different method, based on the MBGR model, predicts even faster decrease of SER per bit than linear. If the increasing number of bits is taken into account, then the SER per chip is not expected to increase faster than linearly with decreasing L/sub G/.