IEEE Transactions on Device and Materials Reliability · 2014 · 12 citations · 10 references
EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesSensorsChip PackagingCmos Circuit DesignImage SensorsIntegrated Circuit DesignIntegrated Circuit DevicesIntegrated Circuit Fabrication3D Integrated CircuitsCmos Fabrication ProcessesCmos Image SensorsCmos ReliabilitySiliconThree-dimensional IntegrationThrough-silicon Via Design
A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon (~ 3.6 μm) and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme.
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A wafer-scale 3-D circuit integration technology
J.A. Burns, Brian F. Aull, C.K. Chen et al. · IEEE Transactions on Electron Devices · 2006 · 269 citations
Through silicon vias technology for CMOS image sensors packaging
David Henry, F. Jacquet, M. Neyret et al. · 2008 · 76 citations