A wafer-scale 3-D circuit integration technology

TLDR

Wafer‑scale 3‑D integrated circuits rely on silicon‑on‑insulator wafers, precise in‑house alignment, low‑temperature bonding, and dense vertical interconnects, while requiring careful placement of the first lithographic level in a stepper process. The paper outlines the rationale and development of this wafer‑scale 3‑D integration technology. The integration process employs four enabling technologies, controls wafer distortion and bow to achieve sub‑micrometer vertical vias, and produces three‑tier digital and analog 3‑D circuits. Performance results include a 3‑D ring oscillator, a 1024×1024 visible imager with 8‑µm pixels, and a 64×64 Geiger‑mode laser radar chip.

Abstract

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described