Cheng-Ta Ko - Concepedia

Author

Cheng-Ta Ko

Industrial Technology Research Institute

Also Known As

Cheng-Ta Ko, Cheng-ta Ko, Jennifer Jaeger

Publications

1.3K

Citations

H-Index

Concepts

All Affiliations

Industrial Technology Research Institute National Yang Ming Chiao Tung University ASM Pacific Technology (China)Indium Corporation (United States)Dow Chemical (United States)

About

Cheng-Ta Ko is an author at Industrial Technology Research Institute specializing in microelectronics, electrical engineering, and electronic packaging.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	20	39	1.1K
2	Electrical Engineering	20	35	1K
3	Computer Engineering	15	20	565
4	Applied Physics	11	11	227
5	Natural Sciences	1	1	14

Cheng-Ta Ko

Publications

1.1K

Citations

H-Index

Page 1

	Year	Citations
Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging John H. Lau, Ming Li, Dewen Tian, IEEE Transactions on Components Packaging and Manufacturing Technology Electrical EngineeringChip-scale PackageEngineeringAdvanced Packaging (Semiconductors)Wafer Scale Processing	2017	147
Fan-Out Wafer-Level Packaging for Heterogeneous Integration John H. Lau, Ming Li, Margie Li Qingqian, IEEE Transactions on Components Packaging and Manufacturing Technology 3D Ic ArchitectureElectrical EngineeringNew Assembly ProcessEngineeringChip-scale Package	2018	83
Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration Cheng-Ta Ko, John H. Lau, Ming Li, IEEE Transactions on Components Packaging and Manufacturing Technology EngineeringEnergy EfficiencyComputer ArchitectureInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors)	2018	47
Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging With Large Chips and Multiple Redistributed Layers John H. Lau, Ming Li, Lei Yang, IEEE Transactions on Components Packaging and Manufacturing Technology EngineeringMechanical EngineeringFowlp FabricationIntegrated CircuitsWafer Scale Processing	2018	46
Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging John H. Lau, Ming Li, Dewen Tian, Electrical EngineeringChip SizeEngineeringChip-scale PackageAdvanced Packaging (Semiconductors)	2017	44
Panel-Level Fan-Out RDL-First Packaging for Heterogeneous Integration John H. Lau, Cheng-Ta Ko, Kai-Ming Yang, IEEE Transactions on Components Packaging and Manufacturing Technology EngineeringEnergy EfficiencyReliability AssessmentMechanical EngineeringIntegrated Circuits	2020	43
Performance and Process Comparison between Glass and Si Interposer for 3D-IC Integration Chun-Hsien Chien, Ching-Kuan Lee, Hsun Yu, IMAPSource Proceedings EngineeringDevice IntegrationProcess ComparisonWafer Scale ProcessingAdvanced Packaging (Semiconductors)	2013	42
Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration Ching-Kuan Lee, Tao‐Chih Chang, Yu-Jiau Huang, EngineeringReliability AssessmentIntegrated CircuitsWafer Scale ProcessingAdvanced Packaging (Semiconductors)	2011	40
Embedded Active Device Packaging Technology for Next-Generation Chip-in-Substrate Package, CiSP Cheng-Ta Ko, Shoulung Chen, Chia-Wen Chiang, 3D Ic ArchitectureElectrical EngineeringDdrii MemoryEngineeringChip-scale Package	2006	35
Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration Cheng-Ta Ko, Chieh-Lin Chang, Jhih-Yuan Pan, EngineeringEnergy EfficiencyComputer ArchitectureAdvanced Packaging (Semiconductors)Heterogeneous Integration	2018	34

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