A. Chou

Record RF performance of 45-nm SOI CMOS Technology

Sungjae Lee, B. Jagannathan, Shreesh Narasimha et al. · 2007 · 179 citations

Electrical Engineering, Engineering, Vlsi Design +12

Hybrid-orientation technology (HOT): opportunities and challenges

Min Yang, V. Chan, K. Chan et al. · IEEE Transactions on Electron Devices · 2006 · 168 citations

Engineering, Silicon Mosfets, Silicon On Insulator +19

Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO₂ gate dielectrics

Min Yang, E. P. Gusev, M. Ieong et al. · IEEE Electron Device Letters · 2003 · 164 citations

Semiconductor Technology, Electrical Engineering, Engineering +13

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Haining Yang, R. Malik, Y. Li et al. · 2005 · 142 citations

Electrical Engineering, Physical Design (Electronics), Engineering +13

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

P. Agnello, T. Ivers, C. Warm et al. · 2006 · 115 citations

Engineering, Vlsi Design, Enhanced Strain +21