Analysis of Die Edge Bond Pads in Hybrid Bonded Multi-Die Stacks

Abstract

The Direct Bond Interconnect (DBI <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> ) Ultra technology is a die-to-wafer (D2W) or die-to-die (D2D) hybrid bonding technology that offers high density Cu-Cu interconnect modules using low processing temperatures. Advances in wafer-to-wafer hybrid bonding technology enabled high volume production of backside-illuminated CMOS images sensors [1] several years ago. Continued development of the supply chain and technology enabled manufacturing of D2W hybrid bonded performance compute modules, for example CPU L3 SRAM [2], [3]. The DBI Ultra D2W technology offers a die-on-tape process that meets the needs of high throughput assembly. The value of the DBI technology can be realized across a wide range of devices and form factors including 2.5 and 3D IC stacking. To proliferate this technology in the industry, it is necessary to define design guidelines and understand the influence of processing and layout interactions.Hybrid bond pad performance is studied as a function of the proximity to the die edge for single die and multi-die stack configurations. The test structures for multi-die stacking analysis are 8 mm x 12 mm die that contain TSVs on a 35 μm pitch which connect to a 15 μm direct bond pad. The direct bond pad array areas include a die center array with 9,480 direct bond interconnects and edge arrays that contain 315 links per column of interconnect. The eight outermost columns of the DBI pad array extend to 80 μm from the die edge.Die stacks ranging from 1-8 die are bonded with the DBI Ultra process at room temperature, followed by an anneal at 250°C. The bond interface is characterized with C-mode scanning acoustic microscopy (CSAM) and the interconnect quality is measured through electrical resistance and cross-sectional scanning electron microscopy (SEM). Die bonding configurations include face to face (DBI pad to DBI pad) and face to back (DBI pad to TSV). The electrical test yield and link resistance are presented as a function of distance from the die edge. Additionally, a set of 5-die stacks is subjected to JEDEC standard temperature cycling and high temperature storage tests for comparison between the edge array bond pads and die center array pads. In all design cases, the resistance data showed little dependence on the distance from the die edge beyond 80 μm indicating a minimal width of the peripheral keep-out-zone, which maximizes the area for active DBI pads.