Buried Power Rails and Nano-Scale TSV: Technology Boosters for Backside Power Delivery Network and 3D Heterogeneous Integration

Abstract

Decoupling signal and power delivery routing to the transistors can be achieved by moving the power wiring to the wafer backside while signal routing is kept in the traditional BEOL of the wafer frontside. This novel concept is gaining a lot of traction to achieve enhanced signal integrity and high quality power delivery performance, and is becoming key for enabling higher gains from further scaling at transistor level while maintaining power savings. To improve the on-chip power delivery, a back-side power delivery network (BSPDN) with nano-through-silicon vias (nano-TSV) directly landing on buried power rails (BPR) of the standard cells has been developed. This novel approach requires extreme wafer thinning to less than 500nm final Si thickness with extremely good thickness control. The nano-TSV are processed from the wafer backside with better than 10nm alignment accuracy to the buried rails, enabling very high-density electrical connections between the backside and frontside of the device wafer. The nano-TSV and buried rail resistances have been characterized for various metallization options including low-resistivity metals as W, Co and Ru, and the manufacturing process has been optimized to reduce the contact resistance between the nano-TSV and the buried rails; measurement results are in good agreement with simulation data.