Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration

TLDR

3D‑SOC integration typically relies on wafer‑to‑wafer bonding with via‑last TSV, and scaling to sub‑500 nm interconnect pitches demands further TSV miniaturization. This work introduces extreme wafer thinning on a carrier followed by nano‑scale via‑last TSV to achieve sub‑500 nm pitch interconnects between a device wafer’s backside and frontside. A sub‑micron thinning process with less than 70 nm total thickness variation was developed, and nano‑TSVs were etched by a Bosch process on 180 × 250 nm top‑CD structures. Electrical testing shows up to 99 % yield of functional backside‑to‑frontside connections.

Abstract

This paper presents a novel approach for extreme wafer thinning on carrier followed by nano-scale via-last formation in order to achieve sub-500nm pitch interconnects, electrically connecting the backside to the frontside of a device wafer. Indeed, it is expected that most of the 3D System-on-Chip (3D-SOC) integration technology schemes will require a wafer-to-wafer (W2W) bonding approach, combined with via-last TSV (Through Silicon Vias) connections. To reach sub-500nm interconnect pitches, via-last TSV scaling is also expected to follow a similar trend. To do so, a dedicated sub-micron wafer thinning process was developed that enables a very tight thickness control over the entire wafer, with less than 70nm total thickness variation (TTV), and nano-TSV's were etched using a Bosch process applied to extremely small CD structures (180x250nm top CD). Functional electrical structures have been measured and characterized, showing up to 99% electrical yielding connections between frontside and backside of the device wafers.