Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration

Anne Jourdain, Filip Schleicher, Joeri De Vos, +10

EngineeringDevice IntegrationExtreme Wafer ThinningExtreme WaferWafer Scale Processing +17

Wafer-Scale Hybrid Integration of InP DFB Lasers on Si Photonics by Flip-Chip Bonding with sub-300nm Alignment Precision

Aleksandrs Marinins, Sebastian Hänsch, Hüseyin Şar, +18

IEEE Journal of Selected Topics in Quantum Electronics

Optical MaterialsEngineeringDevice IntegrationOptical Transmission SystemLaser Applications +21

Localized states in advanced dielectrics from the vantage of spin- and symmetry-polarized tunnelling across MgO

Filip Schleicher, Ufuk Halisdemir, D. Lacour, +21

Nature Communications

Materials ScienceMagnetismSpintronicsSpin DynamicEngineering +10

Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Anshul Gupta, Olalla Varela Pedreira, Goutham Arutchelvan, +54

IEEE Transactions on Electron Devices

EngineeringVlsi DesignIntegrated CircuitsInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors) +14

Disentangling Magnetic Hardening and Molecular Spin Chain Contributions to Exchange Bias in Ferromagnet/Molecule Bilayers

S. Boukari, Hashim Jabbar, Filip Schleicher, +10

Nano Letters

Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network

Rongmei Chen, Melina Lofrano, Gioele Mirabelli, +12

2022 International Electron Devices Meeting (IEDM)

A14 NodeEngineeringEnergy EfficiencyComputer ArchitecturePower Electronics +16

Control of defect-mediated tunneling barrier heights in ultrathin MgO films

D. J. Kim, Woo Seok Choi, Filip Schleicher, +9

Applied Physics Letters

Materials EngineeringMaterials ScienceOptical Absorption SpectroscopyEngineeringTunneling Microscopy +13

28nm pitch single exposure patterning readiness by metal oxide resist on 0.33NA EUV lithography

Danilo De Simone, Luka Ključar, Poulomi Das, +26

Spin-driven electrical power generation at room temperature

Kostantine Katcko, Etienne Urbain, Beata Taudul, +12

Communications Physics

Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

Rongmei Chen, Giuliano Sisto, Anne Jourdain, +13

2021 IEEE International Electron Devices Meeting (IEDM)

Signal RoutingElectrical EngineeringEngineeringVlsi DesignNanoelectronics +11