Design and Analysis of Logic-HBM2E Power Delivery System on CoWoS^® Platform with Deep Trench Capacitor

Abstract

A logic-HBM2E power delivery system on a chip-on-wafer-on-substrate (CoWoS) platform with a deep trench capacitor (DTC) has been designed and analyzed for high performance computing (HPC) applications. The DTC integrated in the silicon interposer of the CoWoS provides the capacitance density of 300 nF/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and low leakage current of <1 fA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The impact of the DTC on power integrity of the logic-HBM2E system is investigated. In the logic core area, the system power delivery network (PDN) impedance and the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> voltage droop for the CoWoS with the DTC are 93% and 72% lower than those without the DTC. For the HBM2E PHY area, the PDN impedance and simultaneously switching noise (SSN) of VDDQ for the CoWoS with the DTC are 76% and 62% lower than those without the DTC. Moreover, 11.2% and 16.6% unit interval (UI) eye margin are obtained at the data rate of 2.8 and 3.2 Gbps, respectively. These demonstrate the new CoWoS platform with the DTC provides superior power integrity (PI) performance and greatly enhances the system performance for the next generation artificial intelligence (AI) and HPC applications.