S. Y. Hou

Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology

S. Y. Hou, W. Chris Chen, Clark Hu et al. · IEEE Transactions on Electron Devices · 2017 · 216 citations

Engineering, Computer Engineering, Electrical Engineering +15

Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2

P. K. Huang, Chin‐Wei Lu, Wen-En Wei et al. · 2021 · 91 citations

Engineering, Computer Engineering, High-performance Computing +17

CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package

Yuchen Hu, Yu-Min Liang, Hsieh-Pin Hu et al. · 2023 · 77 citations

Engineering, Computer Engineering, High-performance Computing +17

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Jason Lin, W.C. Chiou, K.F. Yang et al. · 2010 · 70 citations

Engineering, Computer Engineering, Digital Fabrication +16

Integrated Deep Trench Capacitor in Si Interposer for CoWoS Heterogeneous Integration

S. Y. Hou, Harry Hsia, Chung-Hsien Tsai et al. · 2019 · 55 citations

Engineering, Electrical Engineering, High-performance Computing +17