W.C. Chiou - Concepedia

Author

W.C. Chiou

Taiwan Semiconductor Manufacturing Company (Taiwan)

Also Known As

C.H. Wu, W. C. Chiou, W. C. Chiou, Sr., W.C. Chiou, Wei-Yi Chiou

Publications

826

Citations

H-Index

Concepts

All Affiliations

Taiwan Semiconductor Manufacturing Company (Taiwan)

About

W.C. Chiou is an author at Taiwan Semiconductor Manufacturing Company (Taiwan) specializing in engineering, microelectronics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	12	13	714
2	Electrical Engineering	11	12	666
3	Applied Physics	9	9	405
4	Computer Engineering	8	8	582
5	Natural Sciences	1	1	64

W.C. Chiou

Publications

734

Citations

H-Index

Page 1

	Year	Citations
Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology S. Y. Hou, W. Chris Chen, Clark Hu, IEEE Transactions on Electron Devices EngineeringVlsi DesignDevice IntegrationComputer ArchitectureEye Diagram	2017	202
Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2 P. K. Huang, Chin‐Wei Lu, Wen-En Wei, Artificial IntelligenceEngineeringDevice IntegrationComputer ArchitectureIntegrated Circuits	2021	79
High density 3D integration using CMOS foundry technologies for 28 nm node and beyond Jason Lin, W.C. Chiou, K.F. Yang, EngineeringIntegrated CircuitsInterconnect (Integrated Circuits)Chip Integration StructuresHigh Density 3D	2010	70
3D Multi-chip Integration with System on Integrated Chips (SoIC™) Clark Hu, M.F. Chen, W.C. Chiou, EngineeringDevice IntegrationFinfet TechnologyComputer ArchitectureIntegrated Circuits	2019	68
Ultra High Density SoIC with Sub-micron Bond Pitch Y. H. Chen, Chi‐Ming Yang, Chih-Ting Kuo, EngineeringDevice IntegrationIntegrated CircuitsUltrahigh Density 3DInterconnect (Integrated Circuits)	2020	64
SoIC for Low-Temperature, Multi-Layer 3D Memory Integration M. F. Chen, C. S. Lin, E.B. Liao, Memory Cube IntegrationEngineeringComputer ArchitectureInterconnect (Integrated Circuits)Multi-channel Memory Architecture	2020	48
Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking D.Y. Chen, W.C. Chiou, M.F. Chen, EngineeringComputer ArchitectureIntegrated CircuitsBulk Cmos DevicesInterconnect (Integrated Circuits)	2009	47
Low Temperature SoIC Bonding and Stacking Technology for 12-/16-Hi High Bandwidth Memory (HBM) M. F. Chen, Chung-Hao Tsai, Terry Ku, IEEE Transactions on Electron Devices EngineeringMemory DesignEmerging Memory TechnologyComputer ArchitectureDaisy Chains	2020	44
TSV process optimization for reduced device impact on 28nm CMOS C.L. Yu, Chih‐Yung Chang, Hung-En Wang, Low-power Electronics3D Ic ArchitectureElectrical EngineeringPhysical Design (Electronics)Engineering	2011	25
Heterogeneous Integration of a Compact Universal Photonic Engine for Silicon Photonics Applications in HPC Harry Hsia, Chung-Hao Tsai, K. C. Ting, EngineeringDevice IntegrationIntegrated PhotonicsUniversal Pe StructureProgrammable Photonics	2021	24

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