High density 3D integration using CMOS foundry technologies for 28 nm node and beyond - Concepedia

Concepedia

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High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

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2010

Year

Jason Lin, W.C. Chiou, K.F. Yang, Hun-Hsien Chang, Yu‐Cheng Lin, E.B. Liao, J.P. Hung, Yu-Ming Lin, P.H. Tsai, Yi-Chun Shih,

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EngineeringIntegrated CircuitsInterconnect (Integrated Circuits)Chip Integration StructuresHigh Density 3DWafer Scale ProcessingCmos Foundry TechnologiesAdvanced Packaging (Semiconductors)NanoelectronicsHeterogeneous IntegrationTechnology ChallengesIntegrated Circuit DesignElectronic PackagingCritical 3D3D Ic ArchitectureElectrical EngineeringComputer EngineeringChip AttachmentNm NodeMicroelectronics3D PrintingAdvanced PackagingMicrofabricationThree-dimensional Heterogeneous IntegrationApplied PhysicsThree-dimensional Integrated CircuitsBeyond CmosOptoelectronics3D Integration

Abstract

Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (μ-bump) processes and joining, that form the building blocks for 3D IC technology were developed based on established Si foundry technologies. Test vehicles (TV's) have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme.