Hun-Hsien Chang

A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs

Ming‐Dou Ker, Hun-Hsien Chang, Chung‐Yu Wu · IEEE Journal of Solid-State Circuits · 1997 · 75 citations

Engineering, Computer Engineering, Electrical Engineering +14

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Jason Lin, W.C. Chiou, K.F. Yang et al. · 2010 · 70 citations

Engineering, Computer Engineering, Digital Fabrication +16

Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

Ming-Dou Ker, Chung‐Yu Wu, Hun-Hsien Chang · IEEE Transactions on Electron Devices · 1996 · 67 citations

Engineering, Electrical Engineering, Circuit Theory +9

Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC

Ming‐Dou Ker, Chung‐Yu Wu, Cheng Tao et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1996 · 58 citations

Engineering, Electrical Engineering, Circuit Theory +13

Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking

D.Y. Chen, W.C. Chiou, M.F. Chen et al. · 2009 · 47 citations

Engineering, Computer Engineering, Electrical Engineering +17