Chien-Chun Tsai

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing

Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai et al. · IEEE Journal of Solid-State Circuits · 2020 · 88 citations

Engineering, Computer Engineering, High-performance Computing +17

High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions

Shenggao Li, Mu-Shan Lin, Wei‐Chih Chen et al. · IEEE Open Journal of the Solid-State Circuits Society · 2024 · 44 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

A 7nm 4GHz Arm^®-core-based CoWoS^® Chiplet Design for High Performance Computing

Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai et al. · 2019 · 40 citations

Engineering, Computer Engineering, High-performance Computing +6

A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity

Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang et al. · 2009 · 21 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package

Mu-Shan Lin, Chien-Chun Tsai, Cheng-Hsiang Hsieh et al. · 2016 · 12 citations

Engineering, Computer Engineering, Electrical Engineering +14