A 7nm 4GHz Arm^®-core-based CoWoS^® Chiplet Design for High Performance Computing

Abstract

A dual-chiplet Chip-on-Wafer-on-Substrate (CoWoS <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> ) was implemented in 7nm 15M process. Each SoC chiplet has four Arm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> Cortex <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> -A72 processors operating at 4GHz. The on-die interconnect mesh bus operates above 4GHz at 2mm distance. The inter-chiplet connection features a scalable, 0.56pJ/bit power efficiency, 1.6Tb/s/mm2 bandwidth density, and 0.3V Lowvoltage- In-Package-INterCONnect (LIPINCON <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> ) interface achieving 8Gb/s/pin and 320GB/s bandwidth. Silicon test-chip measurements validate the processor, on-die interconnects and inter-chiplet interface performance. The built-in eye-scan feature shows the inter-chiplet connection achieves 244mV eye-height and 69% UI eye-width.