Electrical characterization of near-interface traps in thermally oxidized and NO-annealed SiO ₂ /4H-SiC metal-oxide-semiconductor capacitors

Abstract

Abstract Conductance method and capacitance-voltage (C-V) measurements are used to detect and analyze the characteristics of traps in thermally oxidized and NO-annealed SiO 2 /4 H-SiC-based metal-oxide-semiconductor (MOS) structures, which have energy levels near the conduction band edge ( E C ) of 4 H-SiC. The near-interface traps (NITs) located within SiO 2 near the SiO 2 /4 H-SiC interface, which have a strong effect on the mobility and reliability of the MOS devices, are separated from the interface traps. According to the bias state of the MOS capacitors, two types of electron exchange mechanisms between the energy level of NITs and E C of 4 H-SiC are proposed. The influence of NITs on the (C-V) and conductance characteristics of the MOS capacitors is studied. The possible effect of NITs on the performance of electronic devices containing a MOS capacitor is predicted.