Proceedings of the IEEE · 1997 · 889 citations · 57 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsNanotechnologySemiconductor DevicesCmos Circuit DesignDevice ScalingIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsNanoelectronicsShort-channel EffectsCmos ScalingDevice Scaling EffectsGate Oxide ScalingScaling Effects In CmosSiliconSilicon-on-insulator CmosSilicon-on-insulator TechnologyThreshold Voltage
Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.
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