Ultra-low cost and high performance 65nm CMOS device fabricated with plasma doping

Abstract

N-type and p-type Plasma Doping (PLAD) process have been developed for fabricating the ultra-shallow junctions (USJ) needed for the 65nm CMOS technology. For the first time, the strong benefit of PLAD compared to ultra-low energy implantations for fabricating sub-25nm USJ is demonstrated when standard activation technique is used. Such plasma-doped USJ were successfully integrated into a conventional 65nm CMOS architecture (no offset spacers, low ramp-rate spike annealing <75/spl deg/C/s) for the Source-Drain Extensions (SDE) doping. Transistors drive currents of 720 /spl mu/A//spl mu/m and 330 /spl mu/A//spl mu/m for NMOS and PMOS respectively are obtained at V/sub dd/=0.9V, I/sub off/=100 nA/ /spl mu/m. In addition, junction leakage current was significantly improved (>1 decade) and junction capacitance was reduced by 15% for NMOS.