B. Duriez - Concepedia

Author

B. Duriez

Taiwan Semiconductor Manufacturing Company (Taiwan)

Also Known As

B. Duriez, Blandine Duriez

Publications

741

Citations

H-Index

Concepts

All Affiliations

Taiwan Semiconductor Manufacturing Company (Taiwan)STMicroelectronics (France)STMicroelectronics (Czechia)KU Leuven Philips (France)

About

B. Duriez is an author at Taiwan Semiconductor Manufacturing Company (Taiwan) specializing in engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	14	19	592
2	Electrical Engineering	14	19	592
3	Applied Physics	13	16	532
4	Computer Engineering	6	6	206
5	Materials Engineering	1	1	17

B. Duriez

Publications

634

Citations

H-Index

Page 1

	Year	Citations
Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling Antoine Cros, K. Romanjek, Dominique Fleury, Cmos ScalingEngineeringVlsi DesignComputer ArchitectureSemiconductor Device	2006	120
Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping M.J.H. van Dal, G. Vellianitis, B. Duriez, IEEE Transactions on Electron Devices Electrical EngineeringEngineeringAspect Ratio TrappingRf SemiconductorNanoelectronics	2014	67
Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs M.J.H. van Dal, G. Vellianitis, G. Doornbos, Materials ScienceElectrical EngineeringLateral Nw FetsEngineeringNanotechnology	2018	45
Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers B. Duriez, G. Vellianitis, M.J.H. van Dal, Semiconductor TechnologyRecord PerformanceElectrical EngineeringSemiconductor DeviceEngineering	2013	44
Demonstration of scaled Ge p-channel FinFETs integrated on Si M.J.H. van Dal, G. Vellianitis, G. Doornbos, Electrical EngineeringEngineeringNanoelectronicsElectronic EngineeringGe Finfet	2012	43
A conventional 45nm CMOS node low-cost platform for general purpose and low power applications F. Arnaud, M.T. Basso, D. Sotta,	2004	42
An Ultralow-Resistance Ultrashallow Metallic Source/Drain Contact Scheme for III–V NMOS R. Oxland, S. W. Chang, Xu Li, IEEE Electron Device Letters Electrical EngineeringSemiconductor DeviceEngineeringSpecific ResistancePhysics	2012	40
Ge n-channel FinFET with optimized gate stack and contacts M.J.H. van Dal, B. Duriez, G. Vellianitis, Electrical EngineeringEngineeringVlsi DesignNanoelectronicsBias Temperature Instability	2014	32
First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling T. Mérelle, G. Curatola, A. Nackaerts, Electrical EngineeringOptimization GuidelinesEngineeringVlsi DesignVlsi Architecture	2008	25
Low cost 65nm CMOS platform for Low Power &amp; General Purpose applications F. Arnaud, B. Duriez, B. Tavel, Low-power ElectronicsLow PowerElectrical EngineeringAnalog Transistor ParametersVlsi Design	2004	24

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