B. Duriez

Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling

Antoine Cros, K. Romanjek, Dominique Fleury et al. · 2006 · 120 citations

Cmos Scaling, Engineering, Vlsi Design +21

Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping

M.J.H. van Dal, G. Vellianitis, B. Duriez et al. · IEEE Transactions on Electron Devices · 2014 · 67 citations

Electrical Engineering, Engineering, Aspect Ratio Trapping +10

Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs

M.J.H. van Dal, G. Vellianitis, G. Doornbos et al. · 2018 · 45 citations

Materials Science, Electrical Engineering, Lateral Nw Fets +14

Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers

B. Duriez, G. Vellianitis, M.J.H. van Dal et al. · 2013 · 44 citations

Semiconductor Technology, Record Performance, Electrical Engineering +14

Demonstration of scaled Ge p-channel FinFETs integrated on Si

M.J.H. van Dal, G. Vellianitis, G. Doornbos et al. · 2012 · 43 citations

Electrical Engineering, Engineering, Nanoelectronics +10