Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs

Abstract

We present (i) a novel, thermally stable Atomic Layer Deposition (ALD) high-k dielectric stack that, for the first time, has the potential to meet all gate stack requirements for both n- and p-channel Ge FETs, (ii) record low contact resistivity for n-Ge/metal contacts using an implant-free contact scheme with successful implementation into a single nanowire (NW) Ge nFET baseline, (iii) single NW Ge pFETs with short-channel effect (SCE) immunity down to 24 nm physical gate length, of which electrical data show excellent agreement with calibrated models and (iv) demonstration of Ge-channel vertically stacked lateral NW FETs using a 300 mm VLSI compatible platform.