Ultra-shallow Junction Engineering

Ultra-Shallow Junction Engineering is a semiconductor fabrication methodology that specifically enables the precise formation of highly confined, nanoscale doped regions in silicon substrates with minimal diffusion, distinguishing itself by addressing the critical challenge of junction depth scaling in advanced complementary metal–oxide–semiconductor (CMOS) technologies.

144

Publications

3.7K

Citations

745

Authors

161

Institutions

Publications per year

2017–2026

2

Authors

745

  1. CL
    C. Laviron

    CEA Grenoble, France

    7 publications · 174 citations

    7

    h-index

  2. TS
    T. Sarnet

    Centre National de la Recherche Scientifique, France

    6 publications · 143 citations

    6

    h-index

  3. MH
    Miguel Hernández

    Commissariat à l'Énergie Atomique et aux Énergies Alternatives, France

    6 publications · 143 citations

    6

    h-index

  4. GK
    G. Kerrien

    Université Paris-Sud, France

    6 publications · 158 citations

    6

    h-index

  5. JB
    J. Boulmer

    Université Paris-Sud, France

    6 publications · 158 citations

    6

    h-index

1–5 of 745

Venues

  1. IEEE Transactions on Electron Devices

    11 publications · 454 citations

    11

    h-index

  2. Materials Science and Engineering B

    13 publications · 294 citations

    10

    h-index

  3. 9

    h-index

  4. Applied Physics Letters

    7 publications · 217 citations

    7

    h-index

  5. Journal of Electronic Materials

    JEM · 7 publications · 201 citations

    7

    h-index

1–5