Ultra-shallow Junction Engineering
Ultra-Shallow Junction Engineering is a semiconductor fabrication methodology that specifically enables the precise formation of highly confined, nanoscale doped regions in silicon substrates with minimal diffusion, distinguishing itself by addressing the critical challenge of junction depth scaling in advanced complementary metal–oxide–semiconductor (CMOS) technologies.
144
Publications
3.7K
Citations
745
Authors
161
Institutions
Publications per year
2017–2026
2
Parents
144
Mizuki Ono, M. Saito, T. Yoshitomi et al. · IEEE Transactions on Electron Devices · 1995 · 114 citations
Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions
Mizuki Ono, M. Saito, T. Yoshitomi et al. · 2002 · 105 citations
Roberto C. Longo, Kyeongjae Cho, W. G. Schmidt et al. · Advanced Functional Materials · 2013 · 98 citations
1–5 of 144
745
7
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6
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Commissariat à l'Énergie Atomique et aux Énergies Alternatives, France
6 publications · 143 citations
6
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6
h-index
6
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1–5 of 745
161

Centre National de la Recherche Scientifique
Paris, France
10 h-index
39 publications
1.2K citations
Toshiba (Japan)
Tokyo, Japan
9 h-index
93 publications
4K citations
Hitachi (Japan)
Tokyo, Japan
8 h-index
35 publications
701 citations
University of California, Berkeley
Berkeley, United States
7 h-index
20 publications
491 citations
Sopra (France)
Paris, France
7 h-index
16 publications
372 citations
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
Paris, France
7 h-index
17 publications
432 citations
IMEC
Leuven, Belgium
7 h-index
36 publications
987 citations
CEA Grenoble
Grenoble, France
7 h-index
17 publications
432 citations
1–8 of 161
11 publications · 454 citations
11
h-index
13 publications · 294 citations
10
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9 publications · 253 citations
9
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7 publications · 217 citations
7
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JEM · 7 publications · 201 citations
7
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1–5