Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions

Abstract

Forty-nanometer gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. To achieve such shallow junctions, a technique of solid-phase diffusion (SPD) from phosphorous-doped silicated glass (PSG) gate sidewalls is used. The resulting 40 nm gate length n-MOSFETs operate quite normally at room temperature. Even in the sub-50 nm region, short-channel effects-V/sub th/ shift and S-factor degradation-are suppressed very well. The impact ionization rate falls significantly as Vd falls below 1.5 V. It is found that, in the case of Vd less than 1.5 V, hot-carrier degradation is not a serious problem even in the sub-50 nm region.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>