C. Fiegna - Concepedia

Author

C. Fiegna

Also Known As

A. Molfese, Bellutti, P., C Fiegna, C. FIEGNA, C. Fiegna, C.. Fiegna, CLAUDIO FIEGNA, Claudio Fiegna, E. Parker, Fiegna, Claudio

282

Publications

3.7K

Citations

H-Index

104

Concepts

All Affiliations

University of Bologna University of Ferrara University of Udine Consorzio Nazionale Interuniversitario per la Nanoelettronica IMEC

About

C. Fiegna is an author at University of Bologna specializing in engineering, applied physics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	31	86	3.2K
2	Applied Physics	29	71	2.9K
3	Natural Sciences	4	4	102
4	Medicine	1	1	18
5	Biochemistry	1	1	18

C. Fiegna

Publications

3.3K

Citations

H-Index

Page 1

	Year	Citations
Investigation of the p-GaN Gate Breakdown in Forward-Biased GaN-Based Power HEMTs Andrea Natale Tallarico, Steve Stoffels, Paolo Magnone, IEEE Electron Device Letters Wide-bandgap SemiconductorElectrical EngineeringEngineeringNanoelectronicsApplied Physics	2016	163
Understanding Quasi-Ballistic Transport in Nano-MOSFETs: Part I—Scattering in the Channel and in the Drain Pierpaolo Palestri, David Esseni, S. Eminente, IEEE Transactions on Electron Devices EngineeringScattering ModelsCharge TransportSemiconductor DeviceSemiconductors	2005	153
Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation C. Fiegna, Yang Yang, E. Sangiorgi, IEEE Transactions on Electron Devices EngineeringUltrathin-body Soi MosfetsSilicon On InsulatorSelf-heating EffectsSemiconductor Device	2008	153
Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application David Esseni, M. Mastrapasqua, G. K. Celler, IEEE Transactions on Electron Devices Electrical EngineeringEngineeringPhysicsNanoelectronicsSoi Transistors	2001	136
An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode David Esseni, M. Mastrapasqua, G. K. Celler, IEEE Transactions on Electron Devices Electrical EngineeringDouble-gate ModeEngineeringSemiconductor DevicePhysics	2003	117
A 40 nm gate length n-MOSFET Mizuki Ono, M. Saito, T. Yoshitomi, IEEE Transactions on Electron Devices Materials ScienceSemiconductorsElectrical EngineeringNm Gate LengthGate Length	1995	114
Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions Mizuki Ono, M. Saito, T. Yoshitomi, SemiconductorsSemiconductor TechnologyElectrical EngineeringElectronic DevicesSub-50 Nm Gate	2002	105
Scaling the MOS transistor below 0.1 μm: methodology, device structures, and technology requirements C. Fiegna, Hiroshi Iwai, T. Wada, IEEE Transactions on Electron Devices Low-power ElectronicsDevice ModelingElectrical EngineeringGate LengthEngineering	1994	99
PBTI in GaN-HEMTs With p-Type Gate: Role of the Aluminum Content on $\Delta V_{\mathrm {TH}}$ and Underlying Degradation Mechanisms Andrea Natale Tallarico, Steve Stoffels, Niels Posthuma, IEEE Transactions on Electron Devices Wide-bandgap SemiconductorSemiconductor TechnologyElectrical EngineeringEngineeringAl Content	2017	97
Simple and efficient modeling of EPROM writing C. Fiegna, F. Venturi, M. Melanotte, IEEE Transactions on Electron Devices EngineeringHandwritingComputer ArchitectureSimulationComputer-aided Design	1991	86

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