Publication | Closed Access
Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation
153
Citations
60
References
2008
Year
EngineeringUltrathin-body Soi MosfetsSilicon On InsulatorSelf-heating EffectsSemiconductor DeviceNanoelectronicsElectronic EngineeringThermodynamicsElectronic PackagingDevice SimulationDevice ModelingElectrical EngineeringBias Temperature InstabilitySoi Layer ThicknessDevice DesignHeat TransferMicroelectronicsShe EffectsApplied PhysicsThermal Engineering
This paper investigates self‑heating effects in nanoscale SOI n‑MOSFETs, using device simulation to analyze how thermal impacts and device‑structure parameters such as SOI layer thickness, BOX thickness, S/D extension length, and elevated S/D region thickness affect operation. The study employs a 2‑D drift‑diffusion electrothermal simulation, calibrated against Monte Carlo models, to analyze self‑heating in nanoscale SOI n‑MOSFETs. Self‑heating becomes significant due to thin silicon layers and low BOX thermal conductivity, raising temperatures under nominal operation, degrading cutoff frequency in very short MOSFETs, and potentially reducing long‑term reliability, though effects are modest and can be mitigated by design.
This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs. A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis. We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs. The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits. The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations. Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability.
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