75 nm damascene metal gate and high-k integration for advanced CMOS devices

B. Guillaumot, X. Garros, F. Lime, +16

Low-power ElectronicsElectrical EngineeringLow IoffEngineeringVlsi Design +12

Innovative Smart Cut™ Piezo On Insulator (POI) Substrates for 5G acoustic filters

E. Butaud, S. Ballandras, Marie Bousquet, +7

Acoustic MethodsElectrical EngineeringEngineeringAcoustic FiltersAcoustic Metamaterial +9

Totally silicided (CoSi/sub 2/) polysilicon: a novel approach to very low-resistive gate (∼2Ω/□) without metal CMP nor etching

B. Tavel, T. Skotnicki, G. Parès, +6

Materials ScienceCosi/sub 2/Electrical EngineeringEngineeringVlsi Design +12

16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation

T. Skotnicki, S. Monfray, C. Julien, +8

Low-power ElectronicsElectrical EngineeringPhysical Design (Electronics)Nanometer MosfetsVlsi Design +13

Smart Cut™ Piezo On Insulator (POI) substrates for high performances SAW components

E. Butaud, B. Tavel, Sylvain Ballandras, +9

Materials ScienceElectrical EngineeringSmart Cut™ PiezoEngineeringMicrofabrication +9

SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels

S. Monfray, T. Skotnicki, B. Tavel, +15

Cosi/sub 2/Electrical EngineeringSon Pmos DevicesEngineeringNanoelectronics +8

Low cost 65nm CMOS platform for Low Power & General Purpose applications

F. Arnaud, B. Duriez, B. Tavel, +38

Low-power ElectronicsLow PowerElectrical EngineeringAnalog Transistor ParametersVlsi Design +8

Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform

B. Tavel, M. Bidaud, N. Emonet, +20

Low-power ElectronicsGate Leakage RequirementsElectrical EngineeringGate OxideEngineering +9

0.248μm/sup 2/ and 0.334μm/sup 2/ conventional bulk 6T-SRAM bit -cells for 45nm node low cost - general purpose applications

F. Arnaud, C. Boccaccio, F. Salvetti, +29

Electrical EngineeringNode Low CostEngineeringVlsi DesignAdvanced Packaging (Semiconductors) +13

Poly-gate replacement through contact hole (PRETCH): a new method for high-K/metal gate and multi-oxide implementation on chip

S. Harrison, P. Coronel, A. Cros, +15

3D Ic ArchitectureElectrical EngineeringPhysical Design (Electronics)EngineeringVlsi Design +12