X. Garros - Concepedia

Author

X. Garros

Commissariat à l'Énergie Atomique et aux Énergies Alternatives ORCID

Also Known As

Garros, X., Garros, Xavier, Pushpendra Kumar, X Garros, X. Garros, X., Garros, XAVIER GARROS, Xavier Garros

198

Publications

2.2K

Citations

H-Index

Concepts

All Affiliations

Commissariat à l'Énergie Atomique et aux Énergies Alternatives Laboratoire d'Électronique des Technologies de l'Information CEA Grenoble Université Grenoble Alpes Institut polytechnique de Grenoble

About

X. Garros is an author at Commissariat à l'Énergie Atomique et aux Énergies Alternatives specializing in engineering, microelectronics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	25	54	1.8K
2	Applied Physics	23	46	1.6K
3	Computer Engineering	14	21	745
4	Natural Sciences	4	4	151
5	Chemical Engineering	1	1	29

X. Garros

Publications

1.8K

Citations

H-Index

Page 1

	Year	Citations
FDSOI devices with thin BOX and ground plane integration for 32nm node and below C. Fenouillet-Béranger, S. Denorme, P. Perreau, Solid-State Electronics 3D Ic ArchitectureElectrical EngineeringEngineeringVlsi DesignThin Box	2009	130
Characterization and modeling of hysteresis phenomena in high K dielectrics C. Leroux, Jérôme Mitard, G. Ghibaud, Electrical EngineeringDielectricsEngineeringVlsi DesignBias Temperature Instability	2005	107
Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond O. Faynot, F. Andrieu, O. Weber, EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsNon Planar Devices	2010	104
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond F. Andrieu, O. Weber, J. Mazurier, EngineeringVlsi DesignIntegrated CircuitsUltra-thin BobyAdvanced Packaging (Semiconductors)	2010	103
3D Sequential Integration: Application-driven technological achievements and guidelines P. Batude, Laurent Brunet, C. Fenouillet-Béranger, Contact PitchEngineering3D ModelingComputer-aided DesignSequential Integration	2017	73
75 nm damascene metal gate and high-k integration for advanced CMOS devices B. Guillaumot, X. Garros, F. Lime, Low-power ElectronicsElectrical EngineeringLow IoffEngineeringVlsi Design	2003	69
Frequency characterization and modeling of interface traps in HfSixOy/HfO2 gate dielectric stack from a capacitance point-of-view Pascal Le Masson, Jean‐Luc Autran, Michel Houssa, Applied Physics Letters Device ModelingSemiconductorsElectrical EngineeringEngineeringSilicon Band Gap	2002	66
New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI C. Fenouillet-Béranger, B. Mathieu, B. Prévitali, EngineeringVlsi DesignNew InsightsIntegrated CircuitsSemiconductor Device	2014	56
Breakthroughs in 3D Sequential technology Laurent Brunet, C. Fenouillet-Béranger, P. Batude, EngineeringComputer Architecture3D ModelingComputer-aided DesignIntegrated Circuits	2018	51
Insights on fundamental mechanisms impacting Ge metal oxide semiconductor capacitors with high-k/metal gate stacks P. Batude, X. Garros, L. Clavelier, Journal of Applied Physics EngineeringCv MeasurementsSemiconductor DeviceSemiconductorsCv Curves	2007	48

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