IEEE Transactions on Semiconductor Manufacturing · 1998 · 23 citations · 16 references
Hardware SecurityPolysilicon Critical DimensionElectrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignCircuit DesignVlsi ArchitectureHardware ReliabilityComputer EngineeringComputer ArchitectureSignal SkewMicroelectronicsCircuit PerformanceCircuit AnalysisCircuit SimulationAnalog Behavioral Modeling
In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 /spl mu/m 64/spl times/8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell.
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