Dennis Ciplickas

A simulation methodology for assessing the impact of spatial/pattern dependent interconnect parameter variation on circuit performance

B.E. Stine, Vikas Mehrotra, Duane S. Boning et al. · 2002 · 31 citations

Engineering, Vlsi Design, Computer Architecture +20

Yield and Reliability Challenges at 7nm and Below

Andrzej J. Strojwas, K.Y.-Y. Doong, Dennis Ciplickas · 2019 Electron Devices Technology and Manufacturing Conference (EDTM) · 2019 · 29 citations

Simulating the impact of pattern-dependent poly-CD variation on circuit performance

B.E. Stine, Duane S. Boning, J.E. Chung et al. · IEEE Transactions on Semiconductor Manufacturing · 1998 · 23 citations

Hardware Security, Polysilicon Critical Dimension, Electrical Engineering +14

Simulating the impact of poly-CD wafer-level and die-level variation on circuit performance

B.E. Stine, Duane S. Boning, Jaeun Chung et al. · 2002 · 20 citations

Electrical Engineering, Physical Design (Electronics), Engineering +13

Predictive yield modeling of VLSIC's

Dennis Ciplickas, Xiaolei Li, Andrzej J. Strojwas · 2002 · 14 citations

Engineering, Predictive Yield Modeling, Yield Prediction +20