Test structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability

Abstract

The performance and variability of transistors with nanometer-scale feature sizes is sensitive to their layout style and environment. This paper describes the use of an enhanced MOS array test structure to provide accurate and precise estimates of the impact of layout on transistor characteristics for an advanced 130nm CMOS technology. Enhanced MOS arrays, combined with statistical analysis of the measurements, provide reliable information on the impact of layout on the transistor characteristics. This can then form the basis for technology development, design rule development and modeling.