Transistor Scaling

Transistor Scaling is a methodological framework in power amplifier design that systematically reduces the physical dimensions and operating parameters of transistors to enhance efficiency, bandwidth, and integration density while maintaining or improving output power and linearity.

590

Publications

36.1K

Citations

2.3K

Authors

476

Institutions

Publications per year

2017–2026

154

Authors

2.3K

  1. JA
    Jesús A. del Alamo

    Massachusetts Institute of Technology, United States

    6 publications · 313 citations

    6

    h-index

  2. KR
    Kaushik Roy

    Purdue University West Lafayette, United States

    6 publications · 462 citations

    6

    h-index

  3. AJ
    Alvin Joseph

    IBM (United States), United States

    6 publications · 304 citations

    6

    h-index

  4. MR
    M. Radosavljević

    Intel (United States), United States

    6 publications · 223 citations

    6

    h-index

  5. SD
    Suman Datta

    Pennsylvania State University, United States

    5 publications · 141 citations

    5

    h-index

1–5 of 2.3K

Venues

  1. IEEE Transactions on Electron Devices

    49 publications · 2.7K citations

    25

    h-index

  2. IEEE Journal of Solid-State Circuits

    18 publications · 1.8K citations

    14

    h-index

  3. IEEE Transactions on Nuclear Science

    13 publications · 486 citations

    12

    h-index

  4. IEEE Electron Device Letters

    13 publications · 477 citations

    12

    h-index

  5. Solid-State Electronics

    10 publications · 312 citations

    10

    h-index

1–5