Pitfalls in delay fault testing

Abstract

In this paper, we examine delay models used in very large scale integration (VLSI) circuit testing. Our study is based on electrical-level simulation experiments. We present a comprehensive analysis of phenomena which significantly affect the actual delays but are not taken into account by the existing models used in testing. Because of these phenomena, for a given path in a circuit, tests commonly considered equivalent may result in different pass/fail decisions. Moreover, contrary to a common assumption, robust tests may fail to detect faults detectable by nonrobust tests. This may happen even in circuits in which all paths are robust testable. Our analysis questions the test quality offered by delay test procedures used so far.